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INICORE’s All Digital Phase Locked Loop (ADPLL) solution is the result of concept knowledge, design experience and application know-how. INICORE created the structured VHDL PLL model for simulation and synthesis to any target technology.
PLLs are widly used in telecom applications for clock recovery, clock generation and clock supervision. The all digital solution needs no external components, is fully programmable and can be started already locked. Different phase detectors (FIFO fill level, phase errors, etc.) are provided and may be adapted to perfectly fit your application.
Block Diagram
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Features:
All Digital PLL
Maximum Jitter: Clk-Period/2
Infinite frequency hold time
Programmable center frequency
Programmable filter characteristics (cut-off frequency, loop gain)
Synthesisable VHDL model
Fully synchronous design
Adaptable phase detector
Scalable oscillator and loop filter
Customizable for special requirements
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